Job title: Senior Verification Engineer
Company: Molex
Job description: Description
Molex (a subsidiary of Koch Industries) is a globally recognized provider of electronic solutions in a wide range of industries, including data communications, consumer electronics, industrial, automotive, commercial vehicle and medical. We offer over 100,000 products, across a variety of industries: Aerospace & Defense, Automotive, Alternative Energies, Consumer/Home Appliances, Commercial Vehicles, Data/Computing, Industrial Automation, Industrial Electrical, Medical, Scientific, Smartphones and Mobile Devices, Solid State Lighting and Telecoms/Networking. Through our collaborative process, we take a multi-dimensional approach that brings together engineers, product designers and manufacturing to ensure the design cycle is smooth and seamless. We have design and manufacturing facilities around the world, with an expert team of problem-solvers who work across borders to help bring your vision to life. With more than 75 years of experience, we lead the industry in R&D investment, striving to develop and deliver innovative, high-quality, reliable solutions that can be customized to meet your needs.
Koch is proud to be an equal opportunity workplace
Sr Verification IC Engineer
The Role:
The Verification Engineer will define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals. He/She will also be responsible for the mixed-signal simulations of the SOC
The key responsibilities of a Verification engineer comprise:
- Define overall verification strategies, methodologies, and simulation environment
- Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.
- Develop, maintain and publish verification specifications.
- Analyze and debug simulation failures
- Generates code coverage and functional coverage report
- Run gate level simulation and debug them.
- Perform the constraint assertion-based verification
Required Qualifications and Skills:
- BS in EE with 3+ years of experience or MS in EE with 1+ year experience
- Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
- Fluent in verification language such asUVM/OVM/System Verilog, Vera, Verilog
- Experience in writing Test-plans and creating directed and random test cases
- Strong scripting skills inPerl, Python, Linux shells etc.
Expected salary:
Location: Bangalore, Karnataka
Job date: Wed, 31 Aug 2022 05:46:45 GMT
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